AMD Zen4 EPYC “Genoa” processor doubles L2 cache capacity to 1MB

AMD's next-generation processor L2 cache for data centers will be 1X larger. According to the GeekBench score library, an unreleased AMD processor with an OPN core of 100-000000479-13 was tested on a validated motherboard called "Quartz". More specifically, it is an engineering sample based on A0 silicon.

The scorebase information shows that this is a 32-core, 64-thread CPU with a base clock of 1.2GHz, which will undoubtedly be higher after the actual launch given the early state of this sample.

The Genoa EPYC CPU has 1MB of L2 cache. The L3 cache has not changed since Milan, remaining at 32MB per small chip (this sample has CCX, with 8 cores each). However, since Genoa will offer up to 96 cores, the maximum size of the L3 cache will still be higher than its predecessor (except for Milan-X with its 3D V-Cache).

In January this year, ExecutableFix has confirmed that this particular sample is part of the Zen4 Genoa series. According to the leaker, there is also a 96-core sample in testing, but we haven't seen it on Geekbench so far.

Author: King
Copyright: PCPai.COM

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